1. Field of the Invention
The present invention relates to a data slicing circuit for binarizing a demodulated signal in a receiving device in a wireless digital data communication system.
2. Description of the Related Art
In wireless digital data communication systems, digital data are modulated onto an analog radio-frequency carrier signal. The demodulated signal is an analog signal that is sliced and sampled to recover the transmitted digital data. Slicing refers to comparing the demodulated signal with a threshold potential to decide whether the demodulated signal represents a ‘1’ or ‘0’ bit.
In one known type of data slicing circuit, the threshold potential is a smoothed value of the demodulated signal itself, obtained from a low-pass filter. Referring to FIG. 1, the high-frequency analog demodulated signal DS output from the demodulator 21 is supplied to a low-pass filter 22 and one input terminal of a comparator 23. The low-pass filter 21 removes high-frequency components from the analog signal and leaves a low-frequency component Vlf, which is supplied to the other input terminal of the comparator 23. The comparator 23 outputs a binary signal D indicating whether the instantaneous level of the demodulated signal DS is above or below the level of the low-frequency component Vlf.
In another known type of data slicing circuit, the threshold potential has a value offset by a fixed amount from the peak level of the demodulated signal. Referring to FIG. 2, the high-frequency analog demodulated signal DS output from the demodulator 31 is supplied to a peak hold circuit 32, which detects and outputs the peak level Vp. A direct-current (DC) offset generator 33 adds a negative DC offset to the peak level to generate the threshold potential Vpo, which is supplied to one input terminal of a comparator 34. The demodulated signal DS is supplied to the other input terminal of the comparator 34. The comparator 34 outputs a binary signal D indicating whether the instantaneous level of the demodulated signal DS is above or below the threshold potential Vpo.
Other examples of conventional data slicing circuits can be found in Japanese Patent Application Publication No. 2001-319422, which uses a low-pass filter, and No. 2001-358780 (or the parent U.S. Pat. No. 6,735,260), which uses maximum and minimum peak detection circuits and sets the threshold potential halfway between the maximum and minimum levels.
A disadvantage of the data slicing circuit in FIG. 1 is that if the demodulated signal includes long segments of data with predominantly just one binary value, the threshold potential approaches the peak or bottom level of the demodulated signal too closely and the error rate rises.
A disadvantage of the data slicing circuit in FIG. 2 is that even if the demodulated signal has a substantially constant maximum peak level, its minimum peak level or bottom level may vary depending on reception conditions. This is particularly true of signals modulated by amplitude shift keying (ASK). It is accordingly difficult or impossible to determine a DC offset that is suitable for all reception conditions.
The data slicing circuit in U.S. Pat. No. 6,735,260 is also unsuitable for reception of this type of signal, with a relatively constant peak level but a varying bottom level, because the optimum threshold potential tends to be closer to stable peak level than to the unstable bottom level.